1. FIELD OF THE INVENTION
The present invention relates to a memory hierarchy system and more particularly to a management table device in said memory hierarchy system, which when an irremediable fault has occurred in an area of the main memory, causes the buffer memory to be substituted for the invalid area of the main memory.
2. DESCRIPTION OF THE PRIOR ART
The capacity and the mounting density of the memory, especially the main memory used in a data processing system are now increasing rapidly with the demand for processing more and more amount of programs and data and with the progress in the technique of producing semiconductor memories. The improvements in the capacity and mounting density add indeed to the data processing capacity of the data processing system, but are necessarily accompanied by the increase in the number of parts used and therefore the degradation of reliability. Accordingly, in view of the significance of the memory in the data processing system, the improvement of reliability has been effected by the use of means having the capability of correcting errors by employing error-correcting codes.
The error-correcting code consists of useful information and redundant information added thereto. The detection and the correction of the failure of a certain number of bits can be performed by checking the redundant information. In most current data processing systems the error of a single bit can be remedied and the error of two bits can be detected by using such an error-correcting code. Although a data processing system can possess a capability for correcting an error consisting of more than one bit by increasing the number of redundant bits, the provision of such a capability is not desirable from the economical point of view since in that case more memory elements have to be used.
In case where an irremediable fault has taken place in the main memory, the usual measures taken are to prohibit a certain area in the main memory including the fault from being accessed by means of software or to eliminate the fault by stopping the data processing system.
In the running of a data processing system, it is not preferable to stop the system even if there is an irremediable fault in the main memory and a fail soft system having a mechanism for separating a part of the data processing system is in strong demand.
In this respect, it is preferable to prohibit a certain area in the main memory including the irremediable fault from being accessed. However, this artifice renders a relatively large area of the main memory, including the fault, useless so that the effective memory area is reduced.
Moreover, fail-soft memory means each of which is provided with an auxiliary memory or an auxiliary memory area defined in itself and with the auxiliary memory or area being substituted for the area of the main memory where a fault is existing, have been proposed by, for example, W. J. Duda et al; U.S. Pat. No. 3,588,830, patented June 28, 1971, "SYSTEM FOR USING A MEMORY HAVING IRREMEDIABLE BAD BITS" and S. D. Harper; U.S. Pat. No. 3,633,175, patented Jan. 4, 1972, "DEFECT-TOLERANT DIGITAL MEMORY SYSTEM".
However, there has not been proposed an effective, fault-free memory system which takes into consideration the organization of memory hierarchy such that a frequently used part of the data on the main memory is held as a copy for rapid access in the buffer memory having a small capacity but operating at high speed.